ie (IE (Interrupt Enable Control Register))

Function

Control the opening or disabling of all interrupt sources, and whether each interrupt source is allowed.

Structure

The interrupt enable control register is divided into two levels. The first level structure is the interrupt enable control EA. Only when the EA is in the interrupt enable state, the interrupt source interrupt request can be enabled. Allowed; when the EA is in the disallowed state, no matter what state the other bits in the IE register are in, the interrupt source interrupt request will not be allowed. The second-level structure is 5 interrupt enable control bits, which correspond to the interrupt requests of the 5 interrupt sources respectively. When the corresponding interrupt enable control bit is 1, the interrupt source interrupt request is allowed.

The address of IE is A8H, bit addressable, and the bit address is AFH~A8H.

Format

D4

The role of everyone:

• EX0: External interrupt 0 enable bit. EX0=1, enable external interrupt 0 interrupt; EX0=0, disable external interrupt 0 interrupt. When EX0=1 (SETB EX0) and an interrupt signal appears on the P3.2 pin of the MCU, the MCU interrupts the execution of the main program and "flys" to the interrupt service subroutine. After the execution is completed, the interrupt return instruction RET is used to return to the main program. Procedures. When EX0=0 (CLR EX0), even if there is an interrupt signal on the P3.2 pin of the MCU, the program will not "fly" from the main program for execution, because at this time the CPU of the MCU is equivalent to "plugging the ears". The interrupt signal on the P3.2 pin is not received at all, but this does not mean that the signal does not exist. If the MCU of the MCU is free to check the IE0 bit in TCON, if it is 1, it means that an interrupt signal has occurred.

• ET0: T0 overflow interrupt enable bit. ET0=1, enable T0 interrupt; ET0=0, disable T0 interrupt.

• EX1: External interrupt 1 enable bit. EX1=1, enable external interrupt 1 interrupt; EX1=0, disable external interrupt 1 interrupt. When EX1=1 (SETB EX1) and an interrupt signal appears on the external P3.3 pin, the MCU CPU will interrupt the main program and execute the corresponding interrupt service subroutine; when EX1=0 (CLR EX1), the external Even if there is an interrupt signal on the P3.3 pin, the CPU of the one-chip computer cannot interrupt the main program and go to the interrupt service subroutine. Therefore, it can be considered that EX0 and EX1 are control bits that determine whether the CPU can feel the interrupt signal on the external pin P3.2P3.3.

• ET1: T1 overflow interrupt enable bit. ET1=1, enable T1 interrupt; ET1=0, disable T1 interrupt.

• ES: Serial interrupt enable bit. ES=1, enable serial port interrupt; ES=0, disable serial port interrupt.

• EA: Total interrupt enable bit. EA=1, the CPU opens interrupts; EA=0, the CPU prohibits all interrupt requests. The always allowed EA is like a master switch. EA is equivalent to the main gate of each water pipe. If the main gate cannot be opened, there will be no water even if the faucets are opened; conversely, if the main gate is opened and the openings are not opened, there will be no water. If we want the signals on the P3.2 and P3.3 pins to interrupt the main program, we must set the EA bit to 0 (CLR EA).

Application

The following figure 1 shows the definition and diagram of the relevant bits of the interrupt enable control register IE and T0 and T1.

The application of the interrupt enable control register in the timer/counter can be seen from Figure 2. Under the condition that the electronic switches ET0, ET1 and IE in the interrupt enable control register IE are all turned on, when T0 When T1 and T1 overflow, the overflow flag bit of the timer/counter is generated high level before entering the interrupt entry address 000BH and 001BH.

How to use

1. Overall assignment: IE=0x81; (enable global interrupt, open external interrupt 0).

2. Single assignment: EA=1; EX0=1; (enable global interrupt, open external interrupt 0).