DDR2 SDRAM

Structure and Features

DDR2 memory has 240 pins (not including positioning slots), notebook memory has 200 pins

The positioning slots of DDR2 memory are located Between the 64th and 65th pins (the reverse side is between the 184th and 185th pins)

DDR2 memory is all in the form of FBGA (Fine Pitch Ball Grid Array) package, which is characterized by the pin of the memory particle chip Below the particles

DDR2 memory requires 1.8V working voltage and 0.9V pull-up voltage (for data lines)

DDR2 memory can read and write at 4 times the speed of the external bus per clock Data, and can run at 4 times the speed of the internal control bus

DDR2 memory mainly uses switching power supply circuits, and a few use voltage regulation methods.

Definition

DDR2 (Double Data Rate 2) SDRAM is a new generation memory technology standard developed by JEDEC (Joint Electronic Equipment Engineering Committee). The biggest difference between it and the previous generation DDR memory technology standard is that although the same uses the clock The rise/fall delay is the basic method of data transmission at the same time, but DDR2 memory has twice the pre-reading capacity of the previous generation DDR memory (ie: 4bit data read pre-fetch). In other words, DDR2 memory can read/write data at 4 times the speed of the external bus per clock, and can run at 4 times the speed of the internal control bus.

In addition, because the DDR2 standard stipulates that all DDR2 memories are packaged in FBGA, unlike the widely used TSOP/TSOP-II package, the FBGA package can provide better electrical performance and heat dissipation It provides a solid foundation for the stable operation of DDR2 memory and the development of future frequencies. Recalling the development of DDR, from the first generation of DDR200 applied to personal computers through DDR266, DDR333 to today’s dual-channel DDR400 technology, the development of the first generation of DDR has reached the limit of technology, and it has been difficult to improve memory through conventional methods. With the development of Intel’s latest processor technology, the front-side bus requires higher and higher memory bandwidth, and DDR2 memory with higher and more stable operating frequencies will be the general trend.

Memory standard parameters

Standard name

Memory clock frequency

< /td>

Period

I/O bus frequency

Data rate

< /td>

Transmission method

Module name

Limit transmission rate

td>

Bit width

DDR2-400

100MHz< /p>

10ns

200MHz

400Million

td>

Parallel

PC2-3200

3200MB/s

64bit

DDR2-533

133MHz

7.5ns

266MHz

533Million

Parallel

PC2-4200,4300

4266MB/s

td>

64bit

DDR2-667

166MHz p>

6ns

333MHz

667Million

Parallel

PC2-5300,5400

5333MB/s

td>

64bit

DDR2-800

200MHz p>

5ns

400MHz

800Million

Parallel

PC2-6400

6400MB/s

64bit

DDR2-1066

266MHz

3.75ns

533MHz

1066Million

Parallel

< p>PC2-8500,8600

8533MB/s

64bit

Differences

DDR2 and DDR

Before understanding the many new technologies of DDR2 memory, let us look at a set of data comparing DDR and DDR2 technologies.

Latency problem

As can be seen from the above table, under the same core frequency, the actual operating frequency of DDR2 is twice that of DDR. This is due to the fact that DDR2 memory has twice the 4BIT pre-read capability of standard DDR memory. In other words, although DDR2, like DDR, uses the basic method of data transmission at the same time as the clock rise delay and fall delay, DDR2 has twice the ability of DDR to pre-read system command data. In other words, under the same operating frequency of 100MHz, the actual frequency of DDR is 200MHz, while DDR2 can reach 400MHz.

In this way, another problem arises: in DDR and DDR2 memory with the same operating frequency, the memory delay of the latter is slower than the former. For example, DDR 200 and DDR2-400 have the same delay, while the latter has twice the bandwidth. In fact, DDR2-400 and DDR 400 have the same bandwidth, they are both 3.2GB/s, but the core operating frequency of DDR400 is 200MHz, and the core operating frequency of DDR2-400 is 100MHz, which means the delay of DDR2-400 It is higher than DDR400.

Packaging and heat generation

The biggest breakthrough point of DDR2 memory technology is actually not that users think twice the transmission capacity of DDR, but the use of lower heat, With lower power consumption, DDR2 can achieve a faster frequency increase, breaking the 400MHZ limit of standard DDR.

DDR memory is usually packaged in TSOP chip. This package can work well at 200MHz. When the frequency is higher, its long pins will produce high impedance and parasitics. Capacitance, which will affect its stability and the difficulty of frequency increase. This is why it is difficult for the core frequency of DDR to break through 275MHZ. And DDR2 memory adopts FBGA package form. Different from the widely used TSOP package, the FBGA package provides better electrical performance and heat dissipation, which provides a good guarantee for the stable operation of DDR2 memory and the development of future frequencies.

DDR2 memory uses 1.8V voltage, which is much lower than the DDR standard 2.5V, which provides significantly smaller power consumption and less heat. This change is significant Significant.

New technologies adopted by DDR2

In addition to the differences mentioned above, DDR2 also introduces three new technologies, which are OCD, ODT and Post CAS.

OCD (Off-Chip Driver): This is the so-called offline drive adjustment. DDR II can improve signal integrity through OCD. DDR II adjusts the pull-up/pull-down resistance value to make the two voltages equal. Use OCD to improve signal integrity by reducing the tilt of DQ-DQS; improve signal quality by controlling voltage.

ODT: ODT is the termination resistor of the built-in core. We know that a large number of terminating resistors are needed on the motherboard using DDR SDRAM to prevent the signal from being reflected at the data line terminal. It greatly increases the manufacturing cost of the motherboard. In fact, different memory modules have different requirements for the termination circuit. The size of the termination resistor determines the signal ratio and reflectivity of the data line. If the termination resistance is small, the data line signal reflection is low but the signal-to-noise ratio is also low; If the termination resistance is high, the signal-to-noise ratio of the data line will be high, but the signal reflection will increase. Therefore, the termination resistance on the motherboard cannot match the memory module very well, and it will affect the signal quality to a certain extent. DDR2 can build in suitable termination resistors according to its own characteristics, so as to ensure the best signal waveform. Using DDR2 can not only reduce the cost of the motherboard, but also get the best signal quality, which is unmatched by DDR.

Post CAS: It is set to improve the utilization efficiency of DDR II memory. In Post CAS operation, the CAS signal (read/write/command) can be inserted one clock cycle after the RAS signal, and the CAS command can remain valid after the additional delay (Additive Latency). The original tRCD (RAS to CAS and delay) is replaced by AL (Additive Latency), which can be set in 0, 1, 2, 3, 4. Since the CAS signal is placed one clock cycle after the RAS signal, the ACT and CAS signals will never collide.

In general, DDR2 uses many new technologies to improve many of DDR's shortcomings. Although it has many shortcomings in terms of high cost and slow latency, I believe that with the continuous improvement and improvement of technology, These problems will eventually be resolved.

DDR2 and DDR3

DDR in brief

DDR memory has 184 pins (not including positioning slot)

DDR memory positioning slot Located between the 52nd and 53rd pins (the reverse side is between the 144th and 145th pins)

DDR memory mostly adopts TSOP II package

DDR memory working voltage 2.5V

p>

The pre-reading capability of DDR memory is one-half of DDR2

Introduction to DDR3

The pin count and packaging method of DDR3 memory is the same as that of DDR2

The DDR3 memory positioning slot is located between pins 72 and 73 (the reverse side is between pins 192 and 193)

DDR3 memory operating voltage 1.5V

DDR3 memory pre Reading capacity is twice that of DDR2

Comparison table attached

DDR

DDR2

DDR3

Voltage VDD

< /td>

2.5V

1.8V

1.5V

I/O interface

SSTL_25

SSTL_18 p>

SSTL_15

Data transfer rate

200~400

400~800

800~2000

Capacity standard

64M~1G

256M~4G

< /td>

512M~8G

CL value

1.5 /2/2.5/3

3/4/5/6

5/6/7/8 p>

Pre-read (Bit)

2

4

8

Number of logical banks< /p>

2/4

4/8

8/16

burst length

2/4/8

4/8

8

Package form

TSOP

td>

FBGA

FBGA

Number of pins (Pin)

184

240

240

< /td>

Related Articles
TOP