Introduction
Address Register (AR) is used to store the address of the memory unit currently accessed by the CPU. Since there is a difference in operating speed between memory and CPU, address registers must be used to maintain address information until the memory read/write operation is completed. The data register DR is used to temporarily store the data to be transmitted between the microprocessor and the memory or the input/output interface circuit. The address register AR and the data register DR also play the role of isolation and buffering between the internal bus and the external bus of the microprocessor.
Structure
The address register adopts a pure register structure. When accessing the main memory or I/O port, the address register stores the currently accessed address, and the data buffer realizes data buffering. The CPU can access different memory units and different I/O ports by modifying the value in the address register.
The address register can be completed by the component lpm_latch latch in the LPM library. The figure is a structural diagram of the address register. The data width of the address register should be consistent with the data width of the program counter. data[7...0] is the data input terminal of the address register, q[7...0] is the data output terminal of the address register, and gate is the control terminal of the address latch. The function of the gate is when the latch control pulse arrives, the data enters the latch at high level, and latches data at low level to keep the output data stable.
Features
When the CPU and memory exchange information, that is, when the CPU stores/fetches data from the memory, or when the CPU reads instructions from the memory, the address register and data must be used Buffer register. Similarly, if we treat the device address of the peripheral device as the address unit of the memory, then when the CPU and the peripheral device exchange information, we also use the address register and the data buffer register.
The structure of the address register is the same as the data buffer register and the instruction register, and a simple register structure is usually used. The storage of information generally adopts the potential-pulse method, that is, the potential input terminal corresponds to the data information bit, and the pulse input terminal corresponds to the control signal. Under the action of the control signal, the information is instantly entered into the register.
8086 address register
8086 has 8 16-bit registers, including stack registers SP and BP, but does not include instruction register IP, control register FLAGS and four segment registers. AX, BX, CX, DX, these four registers can be accessed in bytes; but BP, SI, DI, SP, these four address registers can only be accessed in 16-bit width.
8086 is based on the design of 8080 and 8085 (it has assembly language source code compatibility with 8080), and has a similar set of registers, but it is expanded to 16 bits. The Bus Interface Unit sends instructions to the Execution Unit through a 6-byte prefetch queue, so the fetching of instructions and operation are synchronized-a primitive form of pipeline (8086) The instruction length varies from 1 to 6 bytes).
8086 has four identical 16-bit registers, but they can also be accessed as eight 8-bit registers; and four 16-bit index registers (including stack index). The data register is usually implicitly used by instructions, and a complicated register configuration is required for the temporary value. It provides 64K 8-bit output and input (or 32K 16-bit) ports, and fixed vector interrupts. Most instructions can only access one memory address, so one of the operators must be a scratchpad. The result of the operation will be stored in one of the operators.
The 64-bit address register can store 2 addresses. The basic unit of the memory is Byte. In other words, it supports a maximum of 16EiB memory, and 1EiB is equivalent to 1024GiB. However, current 64-bit CPUs do not have a 64-bit address bus.